DEFINING DDR MEMORY AND DDR DIMM
Monday, January 31, 2000
Just as we are getting more familiar with Rambus memory and PC133 memory, the new word DDR has surfaced. I often get asked "what is DDR?" The simple answer is "Double Data Rate Synchronous DRAM. It doubles the data transfer rate and is twice as fast." Well, what does that mean?
Two and a half years ago (1997), I saw the first DDR memory driven PC at the JEDEC memory committee meeting. At the time, DDR memory was only made and promoted by Samsung. The chipset to drive the motherboard was the VIA M3 with DDR option. The data rate was at 150Mhz. Unfortunately, the motherboard only worked for a couple of hours before it die.
Although the first motherboard with DDR memory did not work very well, it did spurted enough confidence in the semiconductor community to continue to develop DDR into a commercial product. DDR memory committee and task groups were formed to continue and to perfect the memory architecture. Coincidentally, Rambus memory also surfaced at the same time to compete for the glamour.
WHAT IS DDR?
Unlike Rambus that works on a packet data concept, DDR is indeed very similar to the normal Synchronous DRAM. The normal Synchronous DRAM (we now called SDR) was evolved out of the standard DRAM.
The standard DRAM receives its address command in two address words. It is a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the Row Address Strobe (RAS). Following the RAS command is the Column Address Stobe (CAS) for latching the second address word. Shortly after the Ras and Cas strobes, the stored data is valid for reading.
The SDR DRAM combines a clock with the standard DRAM. The Ras, Cas, and also Data valid are enabled on the rising edge of each clock cycle. Due to the clocking, the position of the data and the rest of the signals are now very predictable. Thus that data latch strobes can be positioned very precisely. Since the data valid window is very predictable, the memory is also divided into four banks to allow internal cell pre-charge and pre-fetch. Burst mode is also added to allow consecutive address fetching without repeating the Ras strobe. Continuous Cas strobe would bring out consecutive data as long as they are from the same Row.
DDR memory works very similar to the SDR except that data is read at both leading edge and falling edge of the clock. Thus a single frequency clock can result in a data transfer as fast as twice the frequency of the clock. The new generation of DDR memory will be running at 200Mhz and 266Mhz data rate.
DDR DRAM, THE DESIGN
The first production generation of DDR memory (generally called DDR 1) has a lot of new performance features.
* It is standardized at 4 internal banks to reduce latency (the setup time required for random location access).
* The double data rate architecture is essentially a 2n pre-fetch designed to transfer two data words per clock cycle.
* A DQ Strobe signal is transmitted by the DDR SDRAM during Reads and by the controller during Writes to center-aligned with the data. Output and input data are all referenced to the DQS signal.
* The DDR DRAM operates with a differential clock to minimize noise interference.
* Burst (consecutive data output) mode is programmable to be at 2,4, or 8 burst length.
* A DLL (data lock loop) is included in the chip to help lock and align the internal timing.
* I/O interface are operated at SSTL_2 Class II level at 2.5V together with a Vref reference voltage.
* Some of the early DDR production will be operating on VDD voltage of 3.3V. Eventually, it is expected to migrate to 2.5V once the low voltage technology matures. This will be for power saving purpose.
The standard DDR SDRAM is hosted in a 66pin 400mil TSOP package similar to the standard SDRAM package. The pin pitch is 0.65mm, making it fitted for regular PCB landing pads without special assembly equipment. It is pin compatible design between the 64Mbit chips, the 128Mbit chips, the 256Mbit chips as well as the 512Mbit stack chips. This makes it easy to utilize a universal DIMM PCB.
DDR MODULES AND OPTIONS
The standard DDR memory module is a 184pin DIMM. It looks and feels like standard 168pin SDRAM DIMM with the exception of one notch on the module instead of the usual 2 notches on the SDR module. Length of module is the same 5.25 inches to save precious motherboard space.
The Standardization Committee has decided on two different memory module configurations with DDR memory. The first one is the unbuffered DDR DIMM which is lower cost and will find its way into PC and Internet appliances. The second option is the buffered DDR DIMM that combines on-board PLL and buffers for higher memory density server applications.
The DDR memory design also has included the optional control signal for a set of FET switches on the memory module. This kind of design is for noise isolation between memory outputs used in an environment of very high memory density workstations.
A specific set of SPD (Serial Presence Detect) to be resided in the little EEprom chip has also been defined by the industry standard.
In the future, there will also be 200pin SODIMM modules and 232pin modules that support some niche market models. Nevertheless, basic feature and functions will be the same.
As far as price concern, we predict DDR will start out with a 10-15% premium over SDR at the startup stage. However, due to the almost equal die size and structure, prize parity will be attended quickly. We will see memory vendors consolidating DDR and SDR onto the same die. At that point, the price difference will be minimized.
On the DDR module price, since no special assembly or test equipment is required, we see the production price and selling price will stay relatively low for the standard 184pin unbuffered modules. Some price premium will be charged for the buffered modules as well as special configuration modules.
Since DDR is an evolution device with outstanding performance and low cost, the computer industry will adopt it very fast. We see that it will roam the memory market starting this summer until 2003 when the next generation of memory is to surface.
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