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Defining Tomorrow's Memory Module Tester


Monday, March 1, 1999 (as in EE Magazine Mar'99 by Cecil Ho/ CST)

Memory module tester companies are scrambling to pencil down a super architecture that adapts to all new technologies.

Intro art: RDRAM, PC133, and DDR Memory Modules
INTRO ART: RDRAM PC133 DDR

Without question computer memory is a fast-growing industry. We have migrated through several memory technologies in the last 10 years: Fast Page Mode, extended data-out random access memory (EDORAM), PC66 synchronous dynamic random access memory (SDRAM), and PC100. And while the life span for each new memory gets shorter and shorter, the nominal PC memory size has grown from 8 MB to 16 MB, to 32 MB, and now to 64MB.

Due to the advances in manufacturing technology, price and revenue have dropped tremendously. This profit picture has diminished the capability of memory module manufacturers to purchase expensive new ATE-class memory testers. Instead, module manufacturers are looking for inexpensive testers to provide optimum throughput vs cost ratio.

New Memories

Four new high-speed memory technologies have emerged since last year. The PC133 extends the 100-MHz synchronous DRAM technology to run at 133 MHz. The Rambus memory is being supported by Intel and has an 800 MHz data rate. The Double Data Rate (DDR) synchronous memory is championed by JEDEC and the workstation companies. The Synclink DRAM (SLDRAM) is being endorsed by an industry consortium.

While the verdict is still not in, trying to support all the new memory technologies has created a great challenge for the memory module testing industry. Memory module tester companies are scrambling to pencil down a super architecture that adapts to all new technologies. The new architecture also must be affordable and easy to use.

PC133 SDRAM Module
SDRAM uses a clock to synchronize signal input and output of the memory. The clock is coordinated with the CPU clock so the timing of the SDRAMs and the timing of the CPU are in sync. SDRAM saves time in executing commands and transmitting data which increases the overall performance of the computer. The effective peak bandwidth is 1GB/s for PC133.

The SDRAM module was introduced in 1995 with a clock speed of 66 MHz. It was upgraded to 100MHz when Intel endorsed the PC100 memory bus speed. IBM and Micron Technology are supporting the new PC133 running at 133-MHz clock rate. This will have significant performance improvement over the PC100 system, which has a peak bandwidth of 800MB/s. Since it is an easy migration path, it will stay with the low-end PC market for an interim period.

DDR SDRAM Module
The DDR SDRAM, a faster version of SDRAM, can read data on both the rising and the falling edge of the system clock, which doubles the data rate of the memory chip. As a result, DDR memories have data rates of 200 MHz and 266 MHz with peak bandwidths of 1.6 GB/s and 2 GB/s at clock rates of 100 MHz and 133 MHz, respectively. Since this concept is easy to understand, it likely will be accepted by the market.

Rambus DRAM
Rambus DRAM (RDRAM) is a unique design developed by Rambus Inc. It is also endorsed by Intel as the memory standard for the next generation of Intel PCs.

RDRAM is extremely fast and uses a narrow, high-bandwidth channel to transmit data at speeds about 10 times faster than standard DRAM. Eight-bit data packets are transmitted at 800 MHz and effectively de-multiplexed on the receiver side to reassemble the 64-bit wide data bus for the processor. Peak bandwidth is 1.6GB/s. By minimizing the data width on the bus, the transmission is more manageable at the high clock frequency. RDRAM is a licensed technology so a royalty and license fee must be paid to use the memory.

Synchlink DRAM

SLDRAM is the major competing technology to RDRAM. Backed by a consortium of chip manufacturers, Sychlink extends the SDRAM four-bank architecture to 16 banks and incorporates a new system interface and control logic to increase performance.

It runs an 18-bit data packet comparable to the 8-bit Rambus. The bus speed can be as high as 800 Mb/s per pin. This essentially gives it superior performance. It also is being proposed as an industry standard.

TESTER SUPER ARCHITECHTURE)

Tester Super Architecture

Figure 1 shows a typical architecture for a next-generation tester. It is a modular design to accommodate different memory technologies.

The basic tester is a 133-MHz, real-time SDRAM tester. Real-time testing allows it to test at the fastest throughput possible. Optional test heads accommodate RDRAM, DDR and SLDRAM memory modules.

The block diagram of a typical tester is shown in Figure 2. Although the PC controls the tester hardware, it does not run the tests. Tests are executed using hardware logic to achieve faster throughput.
TYPICAL TESTER ARCHITECTURE

The power supply provides the necessary voltages for the various memory technologies. These include 3.3V for the PC133, 2.5V for DDR, and 1.8V for RDRAM.

Memory address control is handled by the address sequencer. The data algorithmic generator provides the different test patterns necessary to test the DUT. These patterns can be changed on the fly. Data read out of the DUT is compared with the data written into it by the data comparator. Errors that occur during the test are recorded in the error register.

DDR Test Interface

The test interface for the DDR adds a second set of 64-bit data to the data bus. An additional algorithmic generator is installed to double the write data. Another data comparator captures the read back on the falling clock edge.

Direct RDRAM Test Interface

Due to the high RDRAM frequency (800-MHz data rate), it is necessary to use a custom core logic ASIC. The core logic block design is available from Rambus Technologies.
RAMBUS CORE LOGIC TEST ARCHITECTURE

This chip includes the memory controller, the Rambus ASIC Cell (RAC), a custom application interface to the basic tester, and the clock unit that drives the bus at a 400-MHz clock rate and an 800-MHz data rate. See Figure 3.

This chip can be looked at as a gear box that translates the PC100 signals with a 4:1 gear ratio to four times the clock frequency and eight times the data rate. This ASIC also provides the voltage-level translator for the RDRAM voltage level of 1.8V.

The SLDRAM Test Interface

The SLDRAM test interface is similar to the RDRAM interface. A custom ASIC logic block is required to act like a gear box. This gear box translates the 64-bit PC100 memory bus to the 18-bit packets that the SLDRAM requires. Output can be extended to 800 Mb/s per pin.

Tester Software

The test software must provide the following features:

  • Multiple memory technology testing, including PC100, PC133, DDR, RDRAM and SLDRAM.
  • Automatic device and speed identification.
  • Graphical software display to pinpoint faulty device in pictorial form.
  • Ample selection of standard test patterns.
  • Open software architecture to accept user-generated test timing and vectors.
  • Advanced reporting to allow data merging with popular data-base software
  • Self-calibration and self-diagnostics.
  • Test address coverage to 1GB.
  • An easy-to-use minimum learn curve.
  • Extra-soft switches for integration with automation systems.
  • An automatic over current protection algorithm.
  • Built-in redundancy for reliability.
  • A system clock selectable from 66 MHz to 800 MHz.
  • Address line scrambling and de-scrambling.

Conclusion:
Today, the winner of the Next Generation Memory is still not clear. We do not know if RDRAM, DDR, SLDRAM or PC133 will be emerged as the dominant memory. One thing we do know is that the memory module tester companies must be prepared to supply a state-of-the-art test solution. And the time is now.

About the Author:
Cecil C. Ho, founder and President of CST, Inc. "The   Memory Test Solution Company", has been with the memory testing industry for 27 years. He found CST, Inc. in 1983 on the vision that new personal computers would require new test equipment to verify them. Prior to 1983, Cecil worked with General Instruments and Texas Instruments on equipment and test system design. He holds Electrical Engineering Degree from the University of Texas and is a member of JEDEC Memory Chapter and also of Eta Kappa Nu, a national honor society for electrical engineers. Cecil also holds US and international patents on several test technologies.

By: Cecil Ho
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