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WHY EDO AND SDRAM Memory?


Friday, March 1, 1996

As the demand for better performance on the PC increases, the bottlenecks become the system memory bus and the memory buffer on the video graphic card. In order to take full advantage of multimedia motion video and sound, the memory speed (or rather, the memory bandwidth) must be improved.

The two most promising technologies are the EDO (Extended Data Output) memory and the SDRAM (Synchronous DRAM) memory. EDO memory takes a conventional memory chip and modifies its output by adding a simple latch circuit to allow the data to be valid after the column control signal is gone. By doing that, it allows the computer system to speed up the memory access process and improves the system performance by 10% to 15%.

SDRAM memory brings in the system clock to precisely control the timing of data in order for it to be valid. By doing that, it allows smooth interleaving and pipeline pre-fetch of data. This can lead to greater improvement on system performance.

Conventional memory chips operate commonly in a mode called "Fast Page Mode." That means for each Row's address instruction, there can be multiple Column addresses executed for accessing data in the same Row. This essentially allows 70ns DRAM to be accessed on an average of 40ns. In between the Column address executes, however, there is a dead time of about 18ns called the Column Pre-Charge time. During that time, the system cannot read the data reliably. An EDO chip adds a latch circuit to the output of the Fast Page Mode chip to hold the output data valid during the pre-charge time. This essentially allows shortening of the Column address time and the pre-charge time and in turn reduces the memory access time by 10% to 15%.

EDO technology is very similar to the Fast Page Mode since it has the same pin out on the chip. Consequently, it can easily be implemented and has a very low cost factor for the performance. EDO is very likely to see widespread popularity in the industry during 1996 to 1997. SDRAM calls for a more drastic approach. It takes the conventional memory and adds a clock to control the execution at each step. This makes the data available (valid) time totally predictable. Once the data valid is predictable, a system's CPU can be doing other functions while waiting for the memory data to be available. One of the ways to take advantage of this time is to interleave two banks of memory. Once the first bank's address instructions are latched, the CPU can start to set up the second bank's address and then come back at the precise time to receive the valid data output from the first bank. Another method of streamlining would be pipelining of addresses. Since the data valid time is predictable, several addresses can be pre-fetched by using a look-ahead method. This greatly reduces the set up time and the pre-charge time for consecutive access.

Over all, SDRAM can improve a memory's access speed up to 4 times as much and essentially achieves access times of 10ns. Economically speaking, the SDRAM memory approach provides a long term solution in comparison to EDO. The cost of the semi-conductor does not add much cost to the production. As of today, most DRAM manufacturers have committed and are producing some quantity of SDRAM. On the other hand, System chip set logic vendors have also committed to the program and are due to deliver logic to work with the new SDRAM systems

By: Cecil Ho
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CST Inc. Memory Tester DDR Tester
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