Tuesday, April 1, 2003
Getting OEM Acceptance & Robust Performace from DDR Registered Modules
Large memory capacity and high frequency requirement are putting server memories to a test. Registered memory modules are usually used in server applications and these modules are built with address line registers and clock PLL (phase lock loop) to ensure the clock signal integrity. In order to have memory module performed uniformly in the server system environment, clock skew time is extremely important. JEDEC (the memory standard setting committee) has designed a Clock Reference Standard fixture to calibrate the clock skew on registered modules. JEDEC standard also requires memory module manufacturers to compensate for the clock skew difference between batches of DRAM and different module designs. Failing to do so will dim "not acceptable" for OEM computer manufacturers. This article goes into the details to help module manufacturers to understand the importance and to overcome the deficiency.
Why Registered Module?
Servers need very reliable operations. It also require large amount of system memory to process data at a high speed. Normal server has 8 memory slots instead of the 2 memory slots found in most desktop PC. These 8 slots are usually filled to the maximum capacity with 1 Gigabyte of memory per slot resulting in a system memory of 8Gigabytes total. Electrically, the system controller has a heavy burden in driver power to excite all these memory slots. It is like a single horse pulling 8 carriages at the same time.
(Graphic: Single driver driving 8 memory slots)
However, if the 8 carriages are being pulled by 8 horses tided to the common rein, it would be much easier. The register chips on the module are to do exactly that. It takes the address signals and some of the control signals and line them up for synchronization. At the same time, it boosts the driving power. Since the register chips are controlled by the system clock edge, it will have to wait for the next rising clock to align the signals properly. Basically, it will cause a one-clock system time delay.
(Graphic: Register logical timing diagram showing how it works to line up signals)
Since the clock source on the system board also have to drive a lot of modules, driving power is strengthened using a PLL Clock driver. A PLL (phase lock loop) clock driver is a single input/ multiple output device that keeps all the output at relatively identical phase shift.
(Graphic: Basic PLL block diagram)
A Phase Lock Loop consists of three basic elements; VCO (voltage control oscillator), phase comparator and a loop filter. The VCO is a voltage-controlled oscillator that changes it frequency according to the input control voltage. The phase comparator compares the VCO frequency against the reference input frequency and generates an error voltage representing the difference between the VCO frequency and the reference input frequency. This error voltage is then filtered through the loop filter into DC voltage. This voltage is used to move the VCO frequency into the exact frequency and phase as the reference input.
Since the PLL on the Registered DIMM is built with multiple outputs, it becomes a multiple output zero phase shift buffer for the input clock signal.
How does registered DIMM work in a system?
In order to understand the signal driving strength problem, we should first examine the motherboard circuitry. On the address and control lines, there are usually two copies of drivers to ensure that each driver in the system only has to drive 4 memory slots and a maximum of 2 register loads on each module. The system board also utilizes zero delay (PLL) clock driver to split the original clock signal into 8 branches.
On the DIMM module, the address and control lines are routed through the onboard registers to line up the signals with the next rising edge of the clock. The clock signal is routed through a zero delay clock buffer (PLL) before it is distributed to the different chips on the module.
(Graphic: Register DIMM block diagram showing registers and PLL functions)
High frequency operation calls for more constraint
With modules running at high frequencies as 266MHz, 333MHz and 400MHz data rate, signal lines will also have to be balanced so that the signals can arrive the DRAM chip in the proper relationship to the Clock signal. Any uneven line length, transmission line reflection or capacitance effect can render the signals to be out-of-synchronization. That is why JEDEC pays a lot of attention on specifying the "Clock Net" on a memory module.
Let’s look at a typical "Clock Net" of a DDR DIMM module. The module design specification of the registered DIMM describes that each module is to have a PLL. The PLL input is the differential clock signal from the system board. This input signal is terminated with a 120 ohm resistor on board the module. The multiple output of the PLL is to drive a fixed load configuration of two DRAM and another 120 ohm termination resistor. One of the PLL output is to provide clock signal to the two register chips on the module. This clock line is also terminated into a 120 ohm resistor load.
Let’s take a closer look at the clock net structure of the module. The clock net of the PLL feedback path shows there are options to add compensation capacitor to balance the different design of DIMM PCB. The specification diagram actually shows different compensation location for different version of example designs (Raw Card versions). Essentially, the specification implies that different DIMM board design will require different PLL feedback compensation. As a matter of fact, because the difference in chip input capacitance from vendor to vendor and from batch to batch, this compensation capacitor varies. To solve this problem, JEDEC (the industry standardization committee) had resolved to a standardized Clock Reference Board to measure and to determine the amount of compensation required for any specific registered module.
(Graphics: Net Structure of PLL Feedback Path)
What is a Clock Reference Board?
The Clock Reference Board is a JEDEC standard to unify the clock arrival time between different DIMM modules. The board consists of a clock generator and a seven outputs buffer. Four of the clock signals go to the DIMM module socket while other lines go to the on-board industry defined reference net circuit. Oscilloscope waveform measurement is made at the DRAM and compared against the measurement at the reference net for time delay and skew.
(Graphic: Block diagram of DDR Clock Reference Board)
Depending on the design of the PCB, the batch of DRAM chip and the peripheral chips used, the arrival time between the reference net and to the DRAM will be different. This difference affects system operation if not corrected. Through this clock reference measurement, the skew difference will be quantified in pico-seconds.
To correct this pico-second timing error, a small capacitor can be inserted into the feedback path of the PLL to retard the clock timing. This capacitor is usually in the value of 1-3 pico-farad and should vary from batch to batch and from design to design. The usual JEDEC reference designator for this compensation capacitor is C89 on the DIMM PC board.
(Graphic: Picture of RDIMM showing C89)
New PLL with Built-in Compensation
In order to reduce the component count on a DIMM, there are vendors that offer different value of clock skews with their PLL chips. The amount of clock skew comes with the chip is designated by different dash numbers tailored for the specific application. According to the different skew measurement the Clock Reference Board, the module assembler will just insert the proper dash number of PLL component onto the board.
In summary, different register module will require different clock skew compensation in their production. This skew difference depends on the number of ranks, the PCB, the DRAM and the peripheral chips used. The JEDEC designed Clock Reference Board is the tool to determine this clock skew and the compensation. Only a compensated DIMM would work robust in a system. Only a compensated DIMM would be validated and accepted by reputable OEM server manufacturer.
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